Scalable floating body memory cell for memory compilers and method of using floating body memories with memory compilers

ABSTRACT

A floating body SRAM cell that is readily scalable for selection by a memory compiler for making memory arrays is provided. A method of selecting a floating body SRAM cell by a memory compiler for use in array design is provided.

CROSS-REFERENCE

This application claims the benefit of U.S. Provisional Application No. 61/810,433 filed Apr. 10, 2013, which application is hereby incorporated herein, in its entirety, by reference thereto.

FIELD OF THE INVENTION

The present invention relates to semiconductor memory technology. More specifically, the invention relates to a semiconductor device utilizing an electrically floating body transistor and its usage within a memory compiler.

BACKGROUND OF THE INVENTION

Semiconductor memory devices are used extensively to store data. Memory devices can be characterized according to two general types: volatile and non-volatile. Volatile memory devices such as static random access memory (SRAM) and dynamic random access memory (DRAM) lose data that is stored therein when power is not continuously supplied thereto.

A DRAM cell without a capacitor has been investigated previously. Such memory eliminates the capacitor used in the conventional 1T/1C memory cell, and thus is easier to scale to smaller feature size. In addition, such memory allows for a smaller cell size compared to the conventional 1T/1C memory cell. Chatterjee et al. have proposed a Taper Isolated DRAM cell concept in “Taper Isolated Dynamic Gain RAM Cell”, P. K. Chatterjee et al., pp. 698-699, International Electron Devices Meeting, 1978 (“Chatterjee-1”), “Circuit Optimization of the Taper Isolated Dynamic Gain RAM Cell for VLSI Memories”, P. K. Chatterjee et al., pp. 22-23, IEEE International Solid-State Circuits Conference, February 1979 (“Chatterjee-2”), and “dRAM Design Using the Taper-Isolated Dynamic RAM Cell”, J. E. Leiss et al., pp. 337-344, IEEE Journal of Solid-State Circuits, vol. SC-17, no. 2, April 1982 (“Leiss”), each of which are hereby incorporated herein, in their entireties, by reference thereto. The holes are stored in a local potential minimum, which looks like a bowling alley, where a potential barrier for stored holes is provided. The channel region of the Taper Isolated DRAM cell contains a deep n-type implant and a shallow p-type implant. As shown in “A Survey of High-Density Dynamic RAM Cell Concepts”, P. K. Chatterjee et al., pp. 827-839, IEEE Transactions on Electron Devices, vol. ED-26, no. 6, June 1979 (“Chatterjee-3”), which is hereby incorporated herein, in its entirety, by reference thereto, the deep n-type implant isolates the shallow p-type implant and connects the n-type source and drain regions.

Terada et al. have proposed a Capacitance Coupling (CC) cell in “A New VLSI Memory Cell Using Capacitance Coupling (CC) Cell”, K. Terada et al., pp. 1319-1324, IEEE Transactions on Electron Devices, vol. ED-31, no. 9, September 1984 (“Terada”), while Erb has proposed Stratified Charge Memory in “Stratified Charge Memory”, D. M. Erb, pp. 24-25, IEEE International Solid-State Circuits Conference, February 1978 (“Erb”), both of which are hereby incorporated herein, in their entireties, by reference thereto.

DRAM based on the electrically floating body effect has been proposed both in silicon-on-insulator (SOI) substrate (see for example “The Multistable Charge-Controlled Memory Effect in SOI Transistors at Low Temperatures”, Tack et al., pp. 1373-1382, IEEE Transactions on Electron Devices, vol. 37, May 1990 (“Tack”), “A Capacitor-less 1T-DRAM Cell”, S. Okhonin et al., pp. 85-87, IEEE Electron Device Letters, vol. 23, no. 2, February 2002 and “Memory Design Using One-Transistor Gain Cell on SOI”, T. Ohsawa et al., pp. 152-153, Tech. Digest, 2002 IEEE International Solid-State Circuits Conference, February 2002, all of which are hereby incorporated herein, in their entireties, by reference thereto) and in bulk silicon (see for example “A one transistor cell on bulk substrate (1T-Bulk) for low-cost and high density eDRAM”, R. Ranica et al., pp. 128-129, Digest of Technical Papers, 2004 Symposium on VLSI Technology, June 2004 (“Ranica-1”), “Scaled 1T-Bulk Devices Built with CMOS 90 nm Technology for Low-Cost eDRAM Applications”, R. Ranica et al., 2005 Symposium on VLSI Technology, Digest of Technical Papers (“Ranica-2”), “Further Insight Into the Physics and Modeling of Floating-Body Capacitorless DRAMs”, A. Villaret et al, pp. 2447-2454, IEEE Transactions on Electron Devices, vol. 52, no. 11, November 2005 (“Villaret”), “Simulation of intrinsic bipolar transistor mechanisms for future capacitor-less eDRAM on bulk substrate”, R. Pulicani et al., pp. 966-969, 2010 17^(th) IEEE International Conference on Electronics, Circuits, and Systems (ICECS) (“Pulicani”), all of which are hereby incorporated herein, in their entireties, by reference thereto).

Widjaja and Or-Bach describes a bi-stable SRAM cell incorporating a floating body transistor, where more than one stable state exists for each memory cell (for example as described in U.S. Patent Application Publication No. 2010/00246284 to Widjaja et al., titled “Semiconductor Memory Having Floating Body Transistor and Method of Operating” (“Widjaja-1”) and U.S. Patent Application Publication No. 2010/0034041, “Method of Operating Semiconductor Memory Device with Floating Body Transistor Using Silicon Controlled Rectifier Principle” (“Widjaja-2”), which are both hereby incorporated herein, in their entireties, by reference thereto). This is bi-stability is achieved due to the applied back bias which causes impact ionization and generates holes to compensate for the charge leakage current and recombination.

For memory cells to be used in a compiler, the memory cell itself must be a repeatable and robust design which can be made modular and easily scalable to allow the compiler the flexibility to freely adjust the memory array size without complicated scenarios appearing which require complicated solutions to implement

SUMMARY OF THE INVENTION

In one aspect of the present invention, a floating body SRAM cell that is readily scalable for selection by a memory compiler for making memory arrays is provided, the cell comprising: a floating body memory cell comprising: a floating body region configured to be charged to a level indicative of a state of the memory cell, said floating body region having a first conductivity type selected from p-type and n-type conductivity types; a first region in electrical contact with the floating body region; the first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type; a second region in electrical contact with the floating body region and spaced apart from the first region, the second region having the first conductivity type; a second transistor connected to the second region of the floating body memory cell; and a third transistor connected to the second transistor.

In at least one embodiment, the floating body memory cell further includes a third region in electrical contact with the floating body region and spaced apart from the first and second regions, the third region having the first conductivity type.

In at least one embodiment, the second region has multiple contacts electrically connected thereto.

In at least one embodiment, the floating body memory cell further includes a gate positioned between the first and second regions.

In at least one embodiment, the floating body SRAM cell further includes a first gate positioned between the first and second regions and a second gate positioned between the first and third regions.

In at least one embodiment, the second transistor functions as a pull down device and the second transistor is gated by the third transistor.

In at least one embodiment, the floating body memory cell further includes: a third region in electrical contact with the floating body region and spaced apart from the first and second regions, the third region having the first conductivity type; and a fourth transistor electrically connected to the third region.

In at least one embodiment, the floating body SRAM cell further includes a fourth transistor electrically connected to the third region.

In at least one embodiment, the second transistor functions as a pull down device and the second transistor is gated by the third transistor; and a write access transistor is connected to the third region.

In at least one embodiment, the first region is grounded.

In at least one embodiment, the cell is used as a dual port cell.

In another aspect of the present invention, a floating body SRAM cell that is readily scalable for selection by a memory compiler for making memory arrays is provided, the cell including: a floating body memory cell comprising: a floating body region configured to be charged to a level indicative of a state of the memory cell, the floating body region having a first conductivity type selected from p-type and n-type conductivity types; a first region in electrical contact with the floating body region; the first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type; and a second region in electrical contact with the floating body region and spaced apart from the first region, the second region having the first conductivity type; a pull down device having a gate electrically connected to the second region; and a select device electrically connected to the pull down device, the select device being configured to be connected to a read bit line.

In at least one embodiment, the select device is connected to the read bit line and the read bit line is pre-charged such that a state of the floating body region can be read according to whether the read bit line is pulled down when the select device is enabled; wherein if the state of the floating body region is “1”, the pull down device is turned on and when the select device is enabled, the read bit line is pulled down.

In at least one embodiment, the first region is electrically connected to a write bit line, and the floating body memory cell includes a gate positioned between the first and second regions; wherein a write operation to the floating body region is performable through the write bit line in conjunction with a predetermined bias on the gate.

In at least one embodiment, the read bit line has an output of either zero volts or a pre-charged voltage level, depending upon whether the floating body region is in state “1” or state “0”.

In at least one embodiment, the first region is grounded and the SRAM cell further includes a write device connecting a write word line to the second region, wherein pure logic levels are used to read from and write to the floating body region, and enablement of the write device overpowers the floating body region to write to the floating body region.

In at least one embodiment, the floating body SRAM cell further includes: a write bit line electrically connected to the write device; the write bit line being separate and independently operable of the read bit line to allow for dual port functionality.

In at least one embodiment, the floating body SRAM cell further includes a write access transistor connected between a write bit line and the first region.

In another aspect of the present invention, a method of selecting a floating body SRAM cell by a memory compiler for use in array design is provided, the method including: a user inputting preferred design criteria to at least one processor of the memory compiler; the memory compiler evaluating the preferred design criteria by executing at least one algorithm configured to select a preferred floating body SRAM cell based on the design criteria inputs received; determining whether a preferred floating body SRAM cell can be identified based upon the preferred design criteria inputted and the at least one algorithm executed; and selecting the preferred floating body SRAM cell when identifiable, providing the user with an array design requested by the user, wherein the array design employs the preferred floating body SRAM cells; and when a preferred floating body SRAM cell cannot be clearly identified, proving the user with a report identifying floating body SRAM cell types that were eliminated base on the preferred design criteria, proving remaining SRAM cell type choices that were not eliminated and indicating which are preferable for selection; ad requesting the user to adjust the preferred design criteria or provide an override so as to manually select a preferred floating body SRAM cell type.

In at least one embodiment, the floating body SRAM cell types from which the preferred floating body SRAM cell type is selected include: one-transistor floating body SRAM cell, two-transistor floating body SRAM cell, three-transistor floating body SRAM cell, four-transistor floating body SRAM cell, dual-port floating body SRAM cell and pseudo dual port floating body SRAM cell.

According to an aspect of the present invention a floating body memory cell designed for use in conjunction with a memory compiler is described. Also described are methods, criteria and algorithms to utilize floating body memory cells within a memory compiler.

These and other features of the invention will become apparent to those persons skilled in the art upon reading the details of the memory cells, arrays, methods and compilers as more fully described below.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic of a three transistor scalable floating body SRAM cell according to an embodiment of the present invention.

FIG. 1A is a cross section of a known floating body memory cell, according to the prior art.

FIG. 1B is a cross sectional, schematic illustration of a floating body memory cell with a P+ contact, according to an embodiment of the present invention.

FIG. 2 is a schematic of a four transistor scalable floating body SRAM cell according to an embodiment of the present invention.

FIG. 2A is a cross sectional, schematic illustration of a floating body memory cell with two P+ contacts, according to an embodiment of the present invention.

FIG. 2B is a cross sectional, schematic illustration of a floating body memory cell with a P+ contact that has multiple nodes connected to it, according to an embodiment of the present invention.

FIG. 3 is a schematic of a four transistor scalable floating body SRAM cell that includes separate bit lines for read and write, according to an embodiment of the present invention.

FIG. 4 is a schematic of an alternate embodiment of a four transistor scalable floating body SRAM cell that utilizes a floating body memory cell with two P+ contacts and separate bit lines for read and write, according to an embodiment of the present invention.

FIG. 4A is a cross section of a dual gate floating body memory cell with two P+ contacts, according to an embodiment of the present invention.

FIG. 5 is a flow chart indicating a generator selection process which can identify which floating body memory cell technology to select for a memory compiler, according to an embodiment of the present invention.

FIG. 6 illustrates a typical computer system, components of which, or all of which may be employed in a memory compiler according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Before the present memory cells, arrays, compiler and methods are described, it is to be understood that this invention is not limited to particular embodiments described, as such may, of course, vary. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting, since the scope of the present invention will be limited only by the appended claims.

Where a range of values is provided, it is understood that each intervening value, to the tenth of the unit of the lower limit unless the context clearly dictates otherwise, between the upper and lower limits of that range is also specifically disclosed. Each smaller range between any stated value or intervening value in a stated range and any other stated or intervening value in that stated range is encompassed within the invention. The upper and lower limits of these smaller ranges may independently be included or excluded in the range, and each range where either, neither or both limits are included in the smaller ranges is also encompassed within the invention, subject to any specifically excluded limit in the stated range. Where the stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included in the invention.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Although any methods and materials similar or equivalent to those described herein can be used in the practice or testing of the present invention, the preferred methods and materials are now described. All publications mentioned herein are incorporated herein by reference to disclose and describe the methods and/or materials in connection with which the publications are cited.

It must be noted that as used herein and in the appended claims, the singular forms “a”, “an”, and “the” include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to “a cell” includes a plurality of such cells and reference to “the array” includes reference to one or more arrays and/or sub-arrays and equivalents thereof known to those skilled in the art, and so forth.

The publications discussed herein are provided solely for their disclosure prior to the filing date of the present application. Nothing herein is to be construed as an admission that the present invention is not entitled to antedate such publication, as the dates of publication provided may be different from the actual publication dates which may need to be independently confirmed.

DEFINITIONS

The term “threshold voltage” or “Vt”, as used herein, refers to the minimum voltage level required to be applied to the gate of a floating body memory cell in order to turn on the floating body memory cell to allow conduction between the source and drain of the floating body memory cell.

The term “compiler” “memory compiler”, as used herein, refers to a program (and/or computer that executes the program) that takes a source code or set of constraints and creates a memory array design and physical layout comprising a plurality of memory cells based on the source code or constraints. These generated memory arrays can then be used in various application-specific integrated circuits (ASIC) designs and/or full custom designs as seen fit by the user. Memory compilers can be written to utilize a variety of memory technologies such as metal programmable read-only memory (ROM), anti-fuse ROM, static random-access memory (SRAM), erasable, programmable read-only memory (EPROM), Flash memory, etc. Some memory compilers have the ability to freely switch between multiple memory technologies based on the criteria provided.

“Pure logic levels” are voltage levels which are consistent with the supply voltages used within the logic gates and circuits throughout the rest of the device or macro. Typical examples of these voltages would be supplies like Vdd and Gnd. These voltages may be supplied by the end user or generated by some other circuit like a voltage regulator.

DETAILED DESCRIPTION

A memory compiler receives criteria or source code inputted to it and executes one or more algorithms to generate a variety of outputs such as, but not limited to, memory array circuit design, memory array layout, memory array timing model, memory array functional model, timing specifications, and memory array symbol.

The array outputs generated by memory compilers are typically customizable to an extent. The memory array sizes, including page/word size, are usually available as customizable criteria. Timing/performance is also usually a customizable parameter/criterion, which will directly affect layout size depending on the required performance. Tradeoffs between array periphery size and performance are made based on the criteria provided from the user.

For memory cells to be used in a memory compiler, the memory cell itself must be a repeatable and robust design which can be made modular and easily scalable to allow the memory compiler the flexibility to freely adjust the memory array size without complicated scenarios appearing which require complicated solutions to implement.

The present invention provides scalable memory cells based on the use of floating body mechanics. The scalable floating body memories behave similarly to SRAM and are statically stable with two stable states (state 0 and state 1). Also provided are criteria which a compiler can utilize to optimize and select a preferred or ideal floating body technology to be used in a memory design. FIG. 1 is a schematic of a multi-transistor, scalable floating body SRAM cell 100, according to an embodiment of the present invention, which can be used in a compiler. The floating body memory cell (FBMC) is indicated by device 101′. This specific FBMC 101′ has a P+ and N+ terminal for the source/drain connections and is shown in FIG. 1B. The P+ terminal 18′ of FMBC 101′ is connected to the gate 104 of NMOS (n-channel MOSFET (metal-oxide-semiconductor field-effect transistor)) device 102 via line 117. The N+ terminal 16 of device 101′ is connected to the write bit line 114 which is shared among other identical memory cells (FMBC's) 101′ within the same column. The gate 60 of device 101′ is connected to a write word line 111. Device 102 has its source 106 connected to ground and its drain 108 connected to the source 120 of access NMOS transistor 103 via line 118. Device 103 has its gate 122 connected to a read word line 110 which would be shared with other memory cells along the same row. The drain 124 of access device 103 is connected to a read bit line 115 which is shared with other cells 101 along the same column Line 112 is connection to the DNWELL or buried layer 22 of FBMC 101′ and is shared among all cells 101 within a row, column or array. For the purposes of this invention the voltage level of line 112 is positive, preferably about 1.8V to ensure the proper operation of the FBMCs 101, although the present invention is not limited to a voltage level of 1.8V, as other preset positive voltages may alternatively be applied. Terminal 113 is the substrate terminal that connects to the substrate 12 of cells 101. This terminal will be considered to be consistently at ground for the purposes of this invention unless otherwise stated.

FIG. 1A shows a floating body memory cell 101 that has been described for example in Widjaja-1 and Widjaja-2. The cell 101 includes a substrate 12 of a first conductivity type, such as a p-type conductivity type, for example. Substrate 12 is typically made of silicon, but may comprise germanium, silicon germanium, gallium arsenide, carbon nanotubes, or other semiconductor materials known in the art. The substrate 12 has a surface 14. A first region 16 having a second conductivity type, such as n-type, for example, is provided in substrate 12 and is exposed at surface 14. A second region 18 having the second conductivity type is also provided in substrate 12, and is also exposed at surface 14. Second region 18 is spaced apart from the first region 16, as shown. First region 16 and second region 18 may be formed by an implantation process on the material making up substrate 12, according to any of implantation processes known and typically used in the art. Alternatively, a solid state diffusion process may be used to form first region 16 and second region 18.

A buried layer 22 of the second conductivity type is also provided in the substrate 12, buried in the substrate 12, as shown. Buried layer 22 may also be formed by an ion implantation process on the material of substrate 12. Alternatively, buried layer 22 can be grown epitaxially. A floating body region 24 of the substrate 12 having a first conductivity type, such as a p-type conductivity type, is bounded by surface, first and second regions 16,18, insulating layers 26 and buried layer 22. Insulating layers 26 (e.g., shallow trench isolation (STI)), may be made of silicon oxide, for example. Insulating layers 26 insulate cell 101 from neighboring cells 101 when multiple cells 101 are joined in an array. A gate 60 is positioned in between the regions 16 and 18, and above the surface 14. The gate 60 is insulated from surface 14 by an insulating layer 62. Insulating layer 62 may be made of silicon oxide and/or other dielectric materials, including high-K dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide. The gate 60 may be made of polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides.

In another embodiment, the memory cell 101 may be provided with p-type conductivity type as the first conductivity type and n-type conductivity type as the second conductivity type.

Operation of floating body memory cell (FBMC) 101 of FIG. 1A is described, for example in U.S. Pat. No. 8,174,886 to Widjaja et al., which is hereby incorporated herein, in its entirety, by reference thereto. As described by Widjaja et al. U.S. Pat. No. 8,174,886, the FBMC 101 has two distinct stable states which are referred to as state “1” and state “0” throughout this disclosure. State “1” is defined as a stable state where the floating body 24 voltage is at a high voltage such as 0.6V. State “0” is defined as a stable state where the floating body 24 voltage is a low voltage of about 0V, for example between about 0V and 0.1V. A FBMC 101 that is set to be in state “1” will have a high potential at the floating body 24 which in turn will also lower the FBMC threshold voltage better known as Vt. By lowering the Vt of the FBMC 101, the high floating body 24 voltage makes the FBMC 101 easier to conduct by requiring less voltage on the gate 60 to induce conduction between source 16 and drain 18. Alternatively, an FBMC 101 that is set to be in state “0” will have a floating body 24 voltage close to 0V. This state “0” FBMC will have a higher Vt than the State “1” FBMC 101 and thus require a higher bias on the gate 60 in order to turn on this FBMC 101 and allow conduction between source 16 and drain 18 of the FBMC 101.

The FBMC 101′ shown in FIG. 1B has both an N+ region 16 and P+ region 18′. Writing is performed on this device 101′ through the N+ region 16/terminal 114. Reading can be performed on either the N+ region 16/terminal 114 or the P+ region 18′/terminal 117. The P+ region 18′ via terminal 117 is able to readily access the state of the floating body 24, e.g., about 0V or 0.1V for State 0 and about 0.6V for State 1. However care must be taken when accessing through the P+ region 18′ since it is a direct connection to the floating body 24 and can easily disturb the state of the memory cell 101′. Alternatively, the floating body region 24 could be n-type, region 18′ could be N+ and region 16 could be P+.

In FIG. 1 device 102 is used to sense the contents of memory cell 101, 101′. Since the P+ region 18′ of device 101′ is connected to the gate 104 of device 102, the content of FBMC 101′ (i.e., State 1 or State 0) is protected. When the state of device 101′ is at State 0, transistor 102 will be off. When the state of device 101′ is at State 1, the transistor 102 will be turned on. This makes reading straightforward as device 102 will attempt to pass ground any time FBMC 101′ is set to State 1 and device 102 will be off whenever FBMC 101′ is set to state 0. Prior to reading the content of device 101′, read bit line 115 can be pre-charged or set to a high voltage such as 1.8V. To read the contents of the FBMC 101′, the read access transistor 103 can be turned on by applying a high voltage to the read word line 110. If the FBMC 101′ is set to State 1, sense device 102 will turn on and discharge the contents of the read bit line 115 through the read access transistor 103. Alternatively other schemes can be used to sense this memory cell 101′ such as voltage sensing and current sensing of read bit line 115 and the examples provided above are meant for exemplary purposes only.

To write to the FBMC 101, 101′ the write bit line 114 and the write word line 111 are used. Multiple techniques can be utilized to implement a write 1 or write 0 operations such as Gate Induced Drain Leakage (GIDL) or Gate coupling. GIDL can be used to move the cell 101, 101′ to state 1 by driving the write bit line 114 to a positive voltage such as 1.8V, while moving the write word line 111 to a negative voltage such as −1.8V. These conditions will induce a GIDL condition between the high drain/source voltage and the negative gate voltage. Holes will then be injected into the floating body 24 causing the energy bather between State 0 and State 1 to be overcome in the FBMC operation. Care must be taken in selecting voltages to avoid disturbing cells 101, 101′ along the write word line 111 and the write bit line 114. A write 0 can be implemented by driving write bit line 114 to a slightly negative voltage such as −0.3 V and then driving the write word line 111 to a high voltage such as 0.6V. The positive voltage on the write word line 111 will cause the floating body 24 to couple high through the gate 60 of device 101, 101′. As the voltage of the FB 24 of cell 101, 101′ goes higher, holes are then evacuated due to the forward biased PN junction.

The above method has a drawback of requiring two distinctly separate operations to implement a write 0 and a write 1 and thus require a two-step write operation. Alternatively floating body 24 coupling may be used to write both a state 1 and a state 0 which would avoid the need for a two-step write process. To implement this alternative, write word line 111 is taken from low to high (e.g., about 0V to about 1.8V) during the write operation. The write bit line 114 is used to select which state will be written to FBMC 101, 101′. Write bit line 114 is taken high to a voltage such as 1.8V in order to move the FBMC 101, 101′ to State 1. A high voltage on the write bit line 114 causes electrical isolation of the floating body 24 of FBMC 101, 101′. Thus when the write word line 111 moves from 0V to 1.8V, the floating body 24 couples up with the gate 60 causing a transition from State 0 to State 1. Alternatively to write a state 0, the write bit line 114 can be held at a slightly negative voltage such as −0.3V. When the write word line 111 transitions from 0V to 1.8V, the floating body 24 will attempt to couple with the write word line 111. However, due to the negative voltage on write bit line 114, the PN junction between the floating body 24 and the write bit line 114 will forward bias and evacuate holes from the floating body 24. In addition as the write word line 111 transitions from 0V to 1.8V, a channel will develop as the FBMC 101, 101′ turns on. Once the channel develops it will pass the bit line 114 voltage from source to drain. Since the write bit line 114 is being held at a slightly negative voltage, this acts as a shield reducing the coupling ratio between the gate 60 of cell 101, 101′ to the floating body 24 of cell 101, 101′.

Due to the completely independent nature of the read and write access, the embodiment in FIG. 1 can also be used as a dual port memory. Read and write paths for this memory cell are completely decoupled, so this embodiment can support write operations completely independently of read operations or even implement write and read operations simultaneously.

FIG. 2 is a schematic of a multi-transistor, scalable floating body SRAM cell 200, according to another embodiment of the present invention which can be used in a compiler. This embodiment employs a scalable FBMC 201 or 201′, such as shown in FIG. 2A or FIG. 2B, respectively. In this embodiment, ground is applied via line 230 to the source 16 of the FBMC 201, 201′. The P+ terminal 18 of FBMC 201, see FIG. 2B (or 18 and 17 of FBMC 201′, see FIG. 2A) is/are connected via terminals 232 and 233 to two devices, a write access transistor 204 and a read sense device 202. In FIG. 2A, terminal 233 connects to terminal 17 and terminal 232 connects to terminal 18. In FIG. 2B, both terminals 233 and 232 connect to terminal 18. In FIG. 2, the gate 208 of read sense device 202 is shorted, with the drain/source of write access transistor 204 via terminals 232 and 233 so that only a single contact and p+ region are required at terminal 18. FIG. 2 is meant to schematically represent all three of these different possibilities. The write access transistor 204 has drain/source connections between the FBMC P+ region/terminal 18 and the bit line 215. The gate 206 of write access transistor 204 is connected to the write word line 210. The read sense device 202 has its gate 208 connected to the FBMC 201 P+ terminal 18. The source 220 of read sense device 202 is connected to ground while the drain 222 is connected to the read access transistor (which may be an NMOS) 203. The read access transistor 203 has its gate 224 connected to the read word line 211. The source/drain connections are connected between the drain 222 of device 202 and the bit line 215. Terminal 213 is connected to the DNWell or buried layer 22 of cell 201, 201′ which can be connected to a high voltage source to ensure proper bistable operation of the FBMC 201, 201′. Terminal 214 is the substrate connection, connected to substrate 12 and connected to ground.

Operation of the embodiment of FIG. 2 may be performed using pure logic levels on the bit line 215 in combination with the usage of the read and write word lines 211, 210. The read operation is performed in the same manner as in the embodiment described with regard to FIG. 1. Bit line 215 may be pre-charged to a high voltage such as 1.8V and device 202 can be used to sense the state of the FBMC 201, 201′ through read access transistor 203 once read word line 211 has been driven high. Those skilled in the art will appreciate that the sensing example above is meant for exemplary purposes only and that many other sensing schemes may also be employed including but not limited to current sensing and voltage sensing of bit line 215.

The write access transistor 204 is used to write to the FBMC 201, 201′. The desired state voltage is driven to the bit line 215. A low voltage such as 0V may be used to set the FBMC 201, 201′ to State 0, while a high voltage such as 1.8V may be used to set the FBMC 201, 201′ to State 1. To write to the FBMC 201, 201′, the write access transistor 204 is turned on by driving the write word line 210 from low to high. This passes the contents of the bit line 215 to the P+ terminal 18 of the FBMC 201, 201′. This has the effect of directly forcing the floating body 24 of the FBMC 201, 201′ to either a high or low state. After the FBMC 201, 201′ has been written to, the write access transistor 204 may be turned off by transitioning the write word line 210 from high to low.

The ground voltage on the source 16 of the FBMC 201, 201′ biases the FBMC 201, 201′ to ensure the bistable nature of the FBMC 201, 201′. Note that the gate 60 of the FBMC 201, 201′ is not required for the read and write operation of this memory cell 201, 201′ and can be held at a voltage such as ground via line 212. However, it is also possible to use the gate 60 of the FBMC 201, 201′ to assist with read and write operations by allowing for some additional coupling during read and write operations. During a read operation it is possible to slightly boost the floating body 24 voltage to improve the conductivity of sense device 202. During a write operation the gate 60 voltage coupling could be used to help improve the efficiency and speed of the write operation.

Alternate memory cell structures 201 and 201′ as shown respectively in FIG. 2A and FIG. 2B may be employed and used in the embodiment of FIG. 2 as described above. Lines 232 and 233 are independent connections to the write access transistor 206 and read access transistor gate 208. These lines may be connected to independent P+ regions as shown in FIG. 2A (P+ region 17 and P+ region 18) or connected to the same P+ region (P+ region 18) as shown in FIG. 2B. Independent nodes 232 and 233 as shown in FIG. 2A allow for simultaneous read and write access to the cells 201 and 201′. It is also possible to short the source/drain terminal of device 204 to the gate 208 of device 204 prior to connecting to the FB device 201. In this case only a single P+ region would be required as shown in FIGS. 2 and 1B.

FIG. 3 is a schematic of a scalable floating body SRAM cell according to another embodiment of the present invention which can be used in a compiler. This embodiment is similar to the embodiment of FIG. 2 but is different in that it includes a write bit line 316 that is separate from and independently operable of read bit line 315. The read bit line 315 is connected to the read access transistor 203 and the write bit line 316 is connected to the write access transistor 204. This allows for independent paths for read and write. Because of the independent read and write paths, it is possible to emulate a dual port operation with the limitations that only one write operation and one read operation can be applied to the cell 201, 201′ simultaneously. Additional peripheral logic can be applied to implement, cache and arbitrate the ability to perform two simultaneous read or two simultaneous write operations to fully emulate a dual port cell.

FIG. 4 is a schematic of a multi-transistor, scalable floating body SRAM cell 400, according to another embodiment of the present invention, which can be used in a compiler. This embodiment combines the structure of FIG. 1 but uses the full logic level voltages to read and write the cell contents. The memory cell 401 used in FIG. 4 includes two P+ contacts 16 and 18, respectively. An exemplary schematic, cross-sectional view of how this cell 401 may appear is provided in FIG. 4A. An N+ region 417 is connected to ground 473, as shown in FIG. 4A but not shown in FIG. 4. Additionally FIG. 4A indicates a dual gate structure 60 and 61, however for the intents of the embodiment in FIG. 4 we could assume the gate terminals (71 and 70) to be shorted together, although this is not necessary. A representation of the terminals 70 and 71 shorted together is shown in FIG. 4 as combined gate reference number 462 and terminal 111.

Operation of the embodiment in FIG. 4 uses the same read operation as described in regard to the embodiments of FIGS. 1-3. The write operation using the embodiment of FIG. 4 employs a write bit line 415 in a similar manner to use of the write bit line 114 in the embodiment of FIG. 1. However in the embodiment of FIG. 4 there is a write access transistor 402 connected between the write bit line 115 and the FBMC 401 which has a write select line 410 which must be enabled in order to implement a write operation. Write select line 410 may be shared across multiple cells. The connection between the write access transistor 402 and FBMC 401 is through a P+ connection. Since write access transistor 402 is connected through a P+ connection 16 to the floating body 24, write bit line 415 can be actively driven to the desired state (as determined by voltage level, as described above) by enabling the write access transistor 402 to directly force the floating body 24 to the desired state. For example if the FB of cell 401 is at a low potential (low stable state, i.e., state “0”) and it is desired to change the state of FB cell 401 to the high stable state (i.e., state “1), a logic level of Vdd or 1.8V can be applied to the write bit line 415 in conjunction with a high potential such as Vdd to the write access line 415. This would allow for the bit line voltage to directly drive the FB through the write select gate 402 driving the FBMC to State 1. Once the write select voltage is removed from the write select line 410, device 402 will turn off, and the FB voltage of device 401 will remain at a high stable state.

The embodiments listed are not limited to a one-transistor (1T) floating body memory cell. Rather, the embodiments described above can also be used in conjunction with other floating body memory cells such as two-transistor (2T) or dual port floating body memory cells, for example, such as described by Widjaja in International Application No. PCT/US13/26466, titled “Memory Cell Comprising First and Second Transistors and Methods of Operating” and U.S. Patent Application Publication No. 2012/0120752, titled “Dual-Port Semiconductor Memory and First-In First-Out (FIFO) Memory Having Electrically Floating Body Transistor”, which are both hereby incorporated herein, in their entireties, by reference thereto. Read and write access and sense devices will have to be incremented accordingly to allow for the true dual port access.

Beyond the implementation of scalable floating body memory cells to be used in compilers, specific criteria can be used to properly select the ideal floating body memory technology to be used within a memory design. Speed/performance, density, standby power, port access, memory size, reliability, byte size, page size and erase block size are all examples of criteria which can be used to select the preferred floating body memory cells to be used with a memory array design. Examples of the floating body memory cells available for selection may include, but are not limited to: 1T cell, 2T cell, 3T cell, 4T cell, dual port cell, and pseudo dual port cell (where logic circuitry can be used to separate the read and write operations and thus make a memory cell to appear as a dual port memory cell). Individual criteria alone can be used to select a preferred memory cell to be used within a memory compiler. or a combination of criteria can be used to select the preferred memory cell technology for use in making a floating body memory array. For example, in the above exemplary conditions speed/performance may be used to exclude the use of 1T cells for high speed and high performance cells, since the 1T cells require multiple pass write operations, as data must be read and the cell erased prior to writing new data to a 1T array. Further criteria can be used to further eliminate the options for a preferred floating body memory cell array design. However in the case where high density is the desired selected criteria, then the 1T cell may be immediately identified as the ideal choice.

A desired priority of parameters may also be used to select the optimal floating body memory cell for use in making an array. A ranking system can be used to prioritize the importance of the various parameters by rank. For example, the parameter that is most important for the design would have the highest rank, with the second-most important parameter being second ranked, and so forth.

Another example of a selection criterion can be standby power. Different selections of cell size and configuration may be considered based on the standby power requirements.

An example of how the previously mentioned criteria can be used to select a preferred floating body memory cell for use in an array design is provided hereafter. Speed/performance: 2T, 3T and 4T would be available options. 1T would be ruled out since it is the slowest due to the need for it to erase an entire row/page and then re-write the new data.

Density: 1T cell would be the primary option. Rankings would be based on the smaller cells having priority (e.g. 2T, then 3T, then 4T):

Standby power: 2T or 4T would be preferred since these two cells completely isolate the FBMC to avoid potential leakage paths between cells;

Port access: Options here could be single port, dual port or pseudo dual port. This criterion could actually be used as an option to add to any of the current cells as the use of the dual port FBMC may be considered for all memory cells. Pseudo dual port memory cells could be listed as an option which would prioritize the 3T and 4T cells;

Memory size: Larger arrays would probably lean toward the 1T cell for the high density advantage they provide. An argument can also be given for the 4T cell since it is so robust and can easily scale to large bit line and word line dimensions since it has the simplest reading and writing mechanics;

Reliability: 4T cell may be desirable due to the simplicity of the read and write mechanics;

Erase block size/single bit selectivity: This criterion may be used to rule out the 1T cell choice, since it requires a row/page to be erased before being written. This most likely will require a read prior to writing, then an erase, then a re-writing of data. Bit selectivity would suggest the 2T, 3T or 4T cells since all of those options are bit selectable for write operations.

An example of a memory compiler utilizing a selection process for a floating body memory cell is provided in FIG. 5. This flow chart is for exemplary purposes only and is not meant to limit the scope of this invention. To start the process the user at event 502 provides some sort of user input criteria to the compiler. This may occur in many potentially different ways, for example the criteria listed above could be provided as user parameters in the compiler code, another option could be a pop up form which asks the user questions related to the importance of criteria related to the floating body memory cell. The examples above are for exemplary purposes and not meant to limit the methods in which the compiler may obtain user data/preferences. At event 504, the user enables the memory compiler to proceed with the selection process based upon the inputted criteria. An override option can be provided. The override option can be provided through various means such as code entry or form entry. An override can be used to force the compiler to select a specific memory selected by the user, should the user desire this. At event 506 the compiler executes the process to check as to whether an override option has been submitted by the user. If an override option has been inputted, processing goes to event 508, where the floating body memory cell indicated by the override instruction is selected for use in designing and making the array. At event 510, the compiler begins and carries out the generation of the array design using the selected floating body memory cell type (e.g., 1T, 2T, 3T, 4T, dual-port, pseudo dual port, etc.). At event 512 the compiler outputs the floating body memory array having been generated based on the selected floating body memory type, thereby providing the user with the design and physical layout of the floating body memory array, and the process ends at event 514.

Referring back to event 506, if it is determined that an override option has not been submitted by the user, then the compiler evaluates the other user input at event 514 to attempt to determine the best choice of floating body memory cell to select for making the array, based upon the user's inputs. The evaluation process may include processing the input data to find a selected type of floating body memory cell by process of elimination, selecting the cell type that has the greatest number of features selecting those inputted by the user, and/or by other analysis techniques, including, but not limited to average weighting of ranked features for each cell type and then selecting the cell type with the highest weighted average.

At event 516, the compiler determines whether the evaluation process of event 514 has provided a clear solution as to which type of floating body memory cell is to be selected. If the evaluation process did provide a clear solution, then the compiler at event 518 outputs a report to the user which provides the details upon which the selected memory cell type was selected. Optionally, the process may provide the user an opportunity to review the detailed report to determine whether the cell type that has been selected is acceptable. This is indicated by optional event 520 in FIG. 5. If optional event 520 is carried out and the selected cell is acceptable, or if optional event 520 is not included as an option, processing goes to event 510 for array generation as described above.

If optional event 520 is carried out and the cell selection is not acceptable, the user at event 520 can then input a cell override option, and processing returns to event 506, where it is determined that there is a cell override option, and processing goes to event 508, which was described above.

Referring back to event 516, if it is determined that the evaluation process of event 516 did not provide a clear solution, for example when the provided criteria provides multiple potential solutions or possibly even no available solution, then the compiler at event 522 outputs a report to the user that explains which cell type choices were eliminated and upon which user criteria those choices were eliminated. Additionally, the report details which cell types are the best options (those which have not yet been eliminated) and shows the details of the user input that apply to each cell type remaining.

At event 524, the compiler processing prompts the user to adjust the criteria of the original user input or provide an override and rerun the processing. This returns the processing to event 502 where the user adjusts the user input to restart the process.

Thus, if the compiler, upon evaluation of criteria provided by the user, determines a clear solution as to the specific type of floating body memory cell to select for use in making an array, a report is generated explaining why the specific floating body was selected and which criteria influenced the decision.

On the other hand, if there is no clear single solution, a report can be provided to the user explaining why the compiler had trouble selecting a floating body memory cell to use. It can explain which cells were eliminated from the process and which cells were final candidates and what criteria influenced the decision. The user can then either chose to select a specific floating body memory cell to use with the compiler or again adjust the criteria to influence the decision of the generator.

FIG. 6 illustrates a typical computer system, components of which, or all of which may be employed in a compiler according to an embodiment of the present invention. The computer system 700 includes any number of processors 702 (also referred to as central processing units, or CPUs, and, for example, which may be employed in the computer controller of system 100, as well as one or more sub-sections described) that are coupled to storage devices including primary storage 706 (typically a random access memory, or RAM), primary storage 704 (typically a read only memory, or ROM). As is well known in the art, primary storage 704 acts to transfer data and instructions uni-directionally to the CPU and primary storage 706 is used typically to transfer data and instructions in a bi-directional manner Both of these primary storage devices may include any suitable computer-readable media such as those described above. A mass storage device 708 may also be coupled bi-directionally to CPU 702 and provides additional data storage capacity and may include any of the computer-readable media described above. Mass storage device 708 may be used to store programs, data and the like and is typically a secondary storage medium such as a hard disk that is slower than primary storage. It will be appreciated that the information retained within the mass storage device 708, may, in appropriate cases, be incorporated in standard fashion as part of primary storage 706 as virtual memory. A specific mass storage device such as a CD-ROM or DVD-ROM 714 may also pass data uni-directionally to the CPU.

CPU 702 is also coupled to an interface 710 that includes one or more input/output devices such as video monitors, track balls, mice, keyboards, microphones, touch-sensitive displays, transducer card readers, magnetic or paper tape readers, tablets, styluses, voice or handwriting recognizers, or other well-known input devices such as, of course, other computers, any of which may be provided to a user of the compiler for providing inputs and receiving outputs in the process described with regard to FIG. 5, for example. Finally, CPU 702 optionally may be coupled to a computer or telecommunications network using a network connection as shown generally at 712. With such a network connection, it is contemplated that the CPU might receive information from the network, or might output information to the network in the course of performing the above-described method steps. The above-described devices and materials will be familiar to those of skill in the computer hardware and software arts.

The hardware elements described above may implement the instructions of multiple software modules for performing the operations of this invention. For example, instructions/algorithms for use in selecting an optimum choice of floating body memory cell for use in building a memory array may be stored on mass storage device 708 or 714 and executed on CPU 702 in conjunction with primary memory 706. Likewise, algorithms and instructions for design and building of a memory array, based upon a specific type of floating body memory cell and other user inputs may be stored on mass storage device 708 or 714 and executed on CPU 702 in conjunction with primary memory 706.

The embodiments described above use a P+ tap cell. The present invention provides floating body memory cells that are ideal for memory compiler uses in array design, as they are easily scalable and robust in nature with robust operating conditions. Alternatively, an N+ tap cell can be used for a cell having an n-type floating body region 24. In each case, the tap cell is of the same conductivity type as the floating body region, but is more heavily doped.

The embodiment of FIG. 1 uses a three-transistor, with P+ tap of the floating body device 101′ connecting to the gate 104 of pull down device 102. Pull down device 102 is gated with a select device 103. Select device 103 is connected to a read bit line 115.

Read bit line 115 can be pre-charged and then contents can be read depending on if read bit line 115 is pulled down once select transistor 103 is enabled. If the data stored in floating body region 24 is high (i.e., state “1”), the pull down transistor 102 will be turned on. If select gate (device 103) is enabled, bit line 115 will be pulled low.

Region 16 is connected to a write bit line 114. Write operations can be performed to floating body region 24 through the write bit line 114 in conjunction with the gate bias on gate 60. Advantageously with regard to the read path, the output of the read bit line 115 will be either pre-charged voltage or 0V, depending upon the current state of the floating body region 24. Scalability is based on performance here. For larger columns of memory cells, the memory compiler can adjust to either reduce the read speed, or adjust to use a larger cell with a stronger pull down and pass gate.

The embodiment of FIG. 1 can readily be used as a dual port device with separate read and write paths.

The embodiment of FIG. 2 is a four-transistor cell. Region 16 of floating body device 201, 201′ is grounded. Region 18 has two devices 201, 204 connected to it. Two devices 202 and 203 are identical to the read structure 102, 103 in the embodiment of FIG. 1. The added device (such as NMOS) 204 is a write device which connects bit line 215 directly to the P+ tap of device 201, 201′. Advantageously, pure logic levels can be used to read and write this cell, and this helps reduce or avoid the need for additional required generated voltage or additional circuits such as sense amplifier circuits or the like. A write operation simply overpowers the floating body device 201, 201′ once the write select gate 204 is enabled.

The embodiment of FIG. 3 uses separate bit lines 315, 316 for read and write, respectively. This allows for dual port functionality.

The embodiment of FIG. 4 is same as the embodiment of FIG. 1, except that it uses a two-transistor floating body cell instead of a one transistor floating body cell, with the result being a four transistor cell overall. Thus, there is a select gate provided by device 402 between region 16 and the write bit line 415.

While the present invention has been described with reference to the specific embodiments thereof, it should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the invention. In addition, many modifications may be made to adapt a particular situation, material, composition of matter, process, process step or steps, to the objective, spirit and scope of the present invention. All such modifications are intended to be within the scope of the claims appended hereto. 

That which is claimed is:
 1. A floating body SRAM cell that is readily scalable for selection by a memory compiler for making memory arrays, said cell comprising: a floating body memory cell comprising: a floating body region configured to be charged to a level indicative of a state of the memory cell, said floating body region having a first conductivity type selected from p-type and n-type conductivity types; a first region in electrical contact with said floating body region; said first region having a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type; a second region in electrical contact with said floating body region and spaced apart from said first region, said second region having said first conductivity type; a second transistor connected to said second region of said floating body memory cell; and a third transistor connected to said second transistor.
 2. The floating body SRAM cell of claim 1, said floating body memory cell further comprising: a third region in electrical contact with said floating body region and spaced apart from said first and second regions, said third region having said first conductivity type.
 3. The floating body SRAM cell of claim 2, further comprising: a first gate positioned between said first and second regions; and a second gate positioned between said first and third regions.
 4. The floating body SRAM cell of claim 2, wherein: said second transistor functions as a pull down device and said second transistor is gated by said third transistor; and a write access transistor is connected to said third region.
 5. The floating body SRAM cell of claim 1, wherein said second region has multiple contacts electrically connected thereto.
 6. The floating body SRAM cell of claim 1, wherein said floating body memory cell further comprises: a gate positioned between said first and second regions.
 7. The floating body SRAM cell of claim 1, wherein said second transistor functions as a pull down device and said second transistor is gated by said third transistor.
 8. The floating body SRAM cell of claim 1, said floating body memory cell further comprising: a third region in electrical contact with said floating body region and spaced apart from said first and second regions, said third region having said first conductivity type; and a fourth transistor electrically connected to said third region.
 9. The floating body SRAM cell of claim 1, further comprising: a fourth transistor electrically connected to said third region.
 10. The floating body SRAM cell of claim 1, wherein said first region is grounded.
 11. The floating body SRAM cell of claim 1, wherein said floating body SRAM cell is used as a dual port SRAM cell.
 12. A floating body SRAM cell that is readily scalable for selection by a memory compiler for making memory arrays, said cell comprising: a floating body memory cell comprising: a floating body region configured to be charged to a level indicative of a state of the memory cell, said floating body region having a first conductivity type selected from p-type and n-type conductivity types; a first region in electrical contact with said floating body region; said first region having a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type; and a second region in electrical contact with said floating body region and spaced apart from said first region, said second region having said first conductivity type; a pull down device having a gate electrically connected to said second region; and a select device electrically connected to said pull down device, said select device being configured to be connected to a read bit line.
 13. The floating body SRAM cell of claim 12, wherein said select device is connected to said read bit line and said read bit line is pre-charged such that a state of said floating body region can be read according to whether said read bit line is pulled down when said select device is enabled; wherein if said state of said floating body region is “1”, said pull down device is turned on and when said select device is enabled, said read bit line is pulled down.
 14. The floating body SRAM cell of claim 13, wherein said read bit line has an output of either zero volts or a pre-charged voltage level, depending upon whether said floating body region is in state “1” or state “0”.
 15. The floating body SRAM cell of claim 12, wherein said first region is electrically connected to a write bit line, and said floating body memory cell includes a gate positioned between said first and second regions; wherein a write operation to said floating body region is performable through said write bit line in conjunction with a predetermined bias on said gate.
 16. The floating body SRAM cell of claim 12, wherein said first region is grounded; said SRAM cell further comprising: a write device connecting a write word line to said second region; wherein pure logic levels are used to read from and write to said floating body region, and enablement of said write device overpowers said floating body region to write to said floating body region.
 17. The floating body SRAM cell of claim 16, further comprising: a write bit line electrically connected to said write device; said write bit line being separate and independently operable of said read bit line to allow for dual port functionality.
 18. The floating body SRAM cell of claim 12, further comprising a write access transistor connected between a write bit line and said first region. 